CS665 - Computer Architecture

Fall 2013

Instructor: Professor Stephan Olariu
Office: E&CS 3202
Phone: 683-3915

Course Description: CS665 is a graduate core course in computer architecture. The main emphasis will be on identifying and understanding various quantitative aspects of the cost/performance issues involved in all stages of computer architecture design from functional organization to instruction set architecture, to memory hierarchy design, to pipelining and beyond.

Although most of the course gravitates around single-CPU architectures, aspects of multiprocessor architectures will also be discussed.

Material: Tentative topical coverage

• Chapter 1 - Fundamentals of computer design
• Appendix A - Instruction set principles
• Appendix C - Pipelining: basic and intermediate concepts
• Chapter 3 - Instruction-level parallelism
• Chapter 4 - Data-level parallelism
• Appendix B - Review of memory hierarchy
• Chapter 2 - Memory hierarchy design

Text: The textbook used in this class is Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson, Fifth Edition, Elsevier, 2012. Occasionally, we shall refer to additional material from the companion website.

Prerequisite: CS270 - Introduction to Computer Architecture. Please note that CS665 is NOT open to students who have not had CS270 or equivalent.

Grading Scheme: Please note that all tests are in-class events; tests are closed-book, closed notes. However, the students are allowed a one-page summary sheet

• Intermediate Test 1: 20%
• Intermediate Test 2: 30%
• Intermediate Test 3: 30%
• Programming Project 20%

Office Hours: F 3:00pm - 4:15pm

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