CS665 - Computer Architecture

Fall 2011

Instructor: Professor Stephan Olariu
Office: E&CS 3202
Phone: 683-3915

Course Description: CS665 is a graduate core course in computer architecture. The main emphasis will be on identifying and understanding various quantitative aspects of the cost/performance issues involved in all stages of computer architecture design from instruction set, to functional organization, to logic design, to implementation.

Although most of the course gravitates around uni-processor architectures, aspects of multiprocessor architectures will also be discussed.

Material: Tentative topical coverage

• Chapter 1 - Fundamentals of computer design
• Appendix B - Instruction set architecture design principles
• Appendix A - Pipelining: basic concepts
• Chapter 2 - Instruction-level parallelism
• Chapter 3 - Limits on instruction-level parallelism
• Chapter 4 - Multiprocessors and thread-level parallelism
• Appendix C – Basic memory hierarchy
• Chapter 5 - Memory hierarchy design

Text: The textbook used in this class is Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson, Fourth Edition, Elsevier, 2007. Please note that the Fourth Edition differs drastically from the Third Edition. Occasionally, we shall refer to additional material from the companion website.

Prerequisite: CS270 - Introduction to Computer Architecture. Please note that CS665 is NOT open to students who have not had CS270 or equivalent.

Grading Scheme:

• Intermediate Test 1: 30%
• Intermediate Test 2: 20%
• Intermediate Test 3: 30%
• Programming project: 20%

Office Hours: Th 4:30pm - 5:30pm

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