How to manage memory. In the past, this has been the key resource (only after the CPU). Effective solution requires both hardware and software support. Key issues: speed and flexibility.
Much of history of memory management is attempts to cover problem of too little memory. Traditionally (i.e., a long time ago) process could not start execution until complete binary image was available in main memory.
Alternatives:
Single Partitions:
+-------------+ 0
| |
| OS |
| | OS usually loaded in low memory.
+-------------+
| |
| Static |
| |
| User |
| |
| Space |
| |
+-------------+
| Dynamic |
| User |
| Space |
+-------------+
|/////////////|
|/////////////|
|/////////////|
|/////////////|
|/////////////|
|/////////////|
|/////////////|
|/////////////|
+-------------+ Max Mem.
+-------------+ 0
| |
| Static |
| OS | OS usually loaded in low memory.
| Space |
+-------------+
| Dynamic |
| OS Space | |
+-------------+ | Can grow as needed
|/////////////| V
|/////////////|
|/////////////|
|/////////////|
+-------------+
| Dynamic |
| User | ^
| Space | | Can grow as needed
+-------------+ |
| Static |
| User |
| Space |
+-------------+ Max Mem.
pre>
With the invention of a Relocation Register:
+----------+ +---+
| xxx| Rel. Reg. | |
+----------+ | | physical
+---+ logical | physical | |
|CPU|-------------> + ----------------->| | memory
+---+ address address | |
| |
| |
+---+
or base & limit registers:
limit+------+ +----------+ +---+
reg | | | xxx| Rel. Reg. | |
+------+ +----------+ | | physical
+---+ logical | yes | physical | |
|CPU|------> < -----------> + ----------------->| | memory
+---+ address | address | |
| no | |
V | |
error +---+
we have more flexibility. This simplifies system software by delaying BINDING TIME to physical addresses.
Multiple Partitions
+-------------+ 0
| OS |
| Space |
+-------------+ Suppose P1 completes. Then what?
| P1 |
| | Scan job queue for next process to
| | inititate.
| | First fit
+-------------+ Best fit
| P2 | Worst fit
| |
| | Reassignment of memory (after process
+-------------+ complete) usually results in EXTERNAL
| P3 | fragmentation.
+-------------+
|/////////////|
+-------------+ Max. mem
pre
Can address fragmentation problems with garbage compaction/collection (if its worth the overhead). This causes problems with I/O, DMA.
Paging
address +----+
logical ---------------- | |
address / V | |
+---+ +---+---+ +---+---+ | | p: offset into
|CPU|------| p | d | | f | d |---->| | page table
+---+ +---+---+ +---+---+ | | d: offset into
| ^ | | page
| +---+ | | |
| / | | | | |
| p < | | | | |
| \ | | | | |
-----> | f | ----- +----+
| | frames
| |
+---+
page table
Advantage: No external fragmentation. The compiler need have no knowledge that what it treats as, say, a 32-bit address, is treated as a page table offset and a page offset. Does not change this code.
Disadvantage: Size of page tables. INTERNAL fragmentation
HW support (TLB, etc) To avoid two memory refs (remember, relative to CPU speeds, accesses to memory are slow), have small associative memory (also called associative registers and translation look-aside buffers).
Typically a 10% time increase in unmapped memory references.
Too many pages to keep entire page table in associative memory. Only keep those actively referenced.
Example:
effective access time = 0.9 * 110 + 0.1 * 210
= 120
(if hit rate were 0.98, then 112, not very different from 110)
The old Motorola 68030 had a 22 entry Translation Look-aside Buffer;
The old Intel 80486 had 32 TLB's, claimed a hit rate of 0.98.
The more modern schemes use cache memory with as many as 4096 TLB's.
This scheme supports some memory protection and shared memory.
Primary use of shared memory is to keep only one copy of executable memory resident; several different processes can all run the same copy. Each has its own program counter. Also requires a compiler which generates reentrant code: each process has its own memory location for all local variables.
Programs consist of memory related meaningful units. pages (as above) are entirely artificial. Say, ftn1, ftn2, memblock1, memblock2, ..., main. (memblocks may be arrays, set of local variables associated with a particular procedure).
Each address can be of form ( segid, offset ) = ( s, d )
/ +-----+-----+
| | | |
-------> s < | | |
| | | | |
+---+ | \ |limit| base| +----+
|CPU|--> (s,d) | | | | |
+---+ | | | | | |
| +-----+-----+ | |
| / \ | |
| / yes \ | |
-----------> < ------> + -->| |
| | |
|no | |
v | |
trap +----+
This can easily support memory sharing.
Advantage: If routine never called, never loaded.
Problem: Fragmentation (sige segments are of different sizes)
Paged Segmentation
Can combine segmentation and paging by taking the d of above and changing it to (p,d) as in paging.
+---+ +---+---+---+
|CPU|-->| s | p | d |
+---+ +---+---+---+
| |
| ------------------------+----
| V | +---+
| ------------> >= | | |
| | | | | |
| +------+----+ V | | |
| /| | | trap | | |
V s+r | | | | | / +---+ | |
+ ---- < | | | | | | | | |
^ | | | | | | | | | |
| \|length|ptbr|----- t V p+t< | | | |
| r | | | -----> + | | | +-+-+ | |
| | | | \ | f |- |f|d|->| |
STBR +------+----+ | | +-+-+ | |
Segment table +---+ | |
| |
| |
+---+
(Finally) Virtual Memory
Motivations:
Virtual memory gives programs the appearance of access to much larger physical memory than really exists. Performance depends on:
Pages
+---+ +---+-+ +---+
0 | A | 0 | 4 |x| 0 | |
1 | B | 1 | | | 1 | |
2 | C | 2 | 6 |x| 2 | | -----------
3 | D | 3 | | | 3 | | / \
4 | E | 4 | | | 4 | A | |\ /|
5 | . | 5 | 9 |x| 5 | | | ------------ |
6 | . | 6 | | | 6 | C | | A E |
| |
. . . . . . | BC |
| |
n | . | n| | | n | | \ D /
+---+ +----+-+ +---+ ------------
Logical view page ^ main backing store
of memory table | memory (disk)
(program view in mem \ /
flag ------------v-------------
Physical Memory
How do memory references works?
As always, this isn't necessarily easy. Depends in part on architecture of machine.
Overhead of Demand Paging
When page fault occurs:
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