Miscellaneous information:

This schedule may be modified during the term to adjust for contingencies.

 

Please do not put your UIN or SSN on anything that you submit in this class.

 

Flash program to illustrate CPU/Memory interaction:    cpu/memory

 

 

                                                Tentative Schedule for Fall 2006

 

week

Date material is covered.  Assignments are usually due the following week.

Sections

Homework due at 3:20pm always.  Only the first page number of the problems will be given.

 

Assignment and due date

 

Comments:  Study requires you to understand in detail, whereas read allows more slack.

 

1

 Aug 28-30

Read 1.1-1.4 and study the following

Binary and Hex

 

 

Sept 6: Page 37:   1.1-1.28, hw/baseconversions.doc

Key

 

2

 Sept 6

Reading 1.5-1.7 and study Binary add and two's complement

 

 

Sept 11: Page 40:  1.46, 1.48,

addcomplements

Key

 

 

3

 Sept 11-13

Study 2.1-2.6

Lecture 1 Chapter 2

Lecture 2 Chapter 2

 

Sept 18: Page 148, 2.2-2.4, 2.6

Key

 

4

 Sept 18

 

 

 

 

Sept 20

 

Read, 2.7-2.9

Lecture 3 Chapter 2

 

 

 

Test 1

 

Sept 25:  2.29, 2.30

Lecture 2 Chapter 2, has a HW problem in the section on loops.  Turn that in with this assignment.

Key

 

Through section 2.6

Downgraded from study to read.

5

 Sept 25-27

Section 2.10- fig 2.28

 Read Section 2.18

See Lecture 3

Chapter 2 above.

Lecture 1 Appendix B

Oct 2: 2.31, 2.32, 2.37 (move, clear and beq small only).

Key

 

 

 

 

6

 Oct 2-4

Study 3.1-3.3

Study  App B.1-.3

Appendix B

Lecture 2 Appendix B

 

Oct 16: 3.7, 3.9 and B.7, B.8, B.9

    HW on logic

Key

 

7

 

 

 

 

 

 

8

 

 Oct 11

 

 

 

 

 

 

Oct 16

Study sections B.5 and B.4 as directed in the notes.

Lecture 3 Appendix B

 

 

 

Lecture 4 Appendix B

 

Verilog Hw due Oct 23, see link below.

 

 

 

 

 

 

Due Oct 23

Verilog HW

Key

 

 

 

Oct 18

 

Test 2

 

 

Test cover section 2.7 through appendix B3, note this includes sections 3.1-3.3.  Ie weeks 4-6 above. 

 

 

 

 

 

 

9

 Oct 23 -25

 

 

 

 

 

NOTE:

Oct 24 Mid-TERM

 

 

 

Study App B 7,8

Review Lecture 3 above, then start lecture 5 below.

Due Oct 30:  B.13 (ignore the extension to 6 bit comparison),   B.14 (Note that the solution will use two two-input multiplexers to build the network.  ‘Switching network’ = ‘logic diagram’)

Key

 

Last day to drop freely and receive a W grade.  After this date you must have an extenuating circumstance as defined the University catalog to withdraw without receiving a WF.

 

10

Oct 30-Nov 1

 

 Study App B 9

Lecture 5 Appendix B

Lecture 6 Appendix B

 

Due Nov 6:  Home work

The time line has been inserted into problem 10.

Key

 

 

11

 

Nov 6,8

Study App B 10

Lecture 7 Appendix B

 

Due Nov 13:  Homework

Key

 

12

 Nov 13-15

 

 

 

 4.1-4.3

Lecture 1 Chapter 4

Lecture 2 Chapter 4

Lecture 3 Chapter 4

Due Nov 27:  4.1, 4.2, 4.3, 4.7,4.10

Key

 

13

 Nov 20

 Test 3

 

Section Appendix B.4-B.10 and possibly more.

Test Key

 

 

14

 Nov 27-29

 

4.4-4.6

Review test 1 & test 2 material.  Bring your questions.

Dec 6:  4.14, 4.45, 4.46

Key

 

15

 

 

 

 

 

 

 

 

16

 Dec 4,6

 

 

 

 

 

 

 

 

Dec 11

Questions from test 3 material.  Bring your questions

CPU Cycle review

Enjoy your final next Monday.

 

 

 

 

 

 

 

 

Final

Monday, 3:45-6:45 pm

Comprehensive Exam