Department of Modeling Simulation and Visualization Engineering Thursday, February 4, 2016 12:30 PM, ECSB 1310 Joint Frequency Scaling of Processor and DRAM Dr. Vaibhav Sundriyal Research Scientist Department of Modeling, Simulation, and Visualization Engineering Abstract: Energy efficiency and energy-proportional computing have become a central focus in modern supercomputers. Many previous energy-saving strategies have focused solely on the CPU while the DRAM subsystem has not been addressed sufficiently, even though memory consumes about 20% of the total power in a typical server platform. The proposed runtime system that scales the frequency of both processor and DRAM based on the performance and power models, achieves energy efficiency at both the levels. Specifically, first, a performance-loss constraint is chosen for an application, then, an optimal processor--DRAM frequency pair is modeled such that the pair minimizes the energy consumption in a given time slice. The proposed runtime system has been validated on both single- and multi-threaded benchmarks and results depict significant energy savings with minor performance degradation. Biosketch: Dr. Sundriyal is working as a research scientist at ODU research foundation. Received his B.Tech in Electronics and Communication from Vellore Institute of Technology in India. He joined Iowa State University in Fall 2009 and received his Ph.D. In Fall 2013. He worked as a post-doctoral research associate at Iowa State University and ODU Research Foundation prior to his current assignment. His research interests include high-performance computing, computer architecture and design of energy and power aware runtime system.