Graphics hardware is explained using the SGI Iris as an example. Today's SGI machines have the functional pieces shown in the handout (96KB gif) in a integrated chip instead of an adapter card, but the functionality is basically the same.

The DB is traversed by the CPU, watch out for the trappings of pure parallelism here. See if you can match the rendering pipeline with the hardware components found on this card. The geometry pipeline is made from the first 4 geometry processors (the "Conversion to Integer" processor is no longer used, it's purpose was anti-aliasing).

Notice the pixel cache. This is for feeding raw pixels that do not require geometry processing (eg a video feed) to the image processors.

The pixel bus marks the transition from pipeline design to pure parallelism. The span processors are basically traffic cops shepparding 20 pixels at a time to the appropriate image engine (5 buses to 4 image engines each).

The image engines are where the real work happens (remember Phong shading, ray tracing?). These rasterize their pixels which are stored in the VRAM.

The multimode graphics processors, lookup tables and DACs comprise the video adaptor which constructs and feeds the signals to the monitor.