Main Memory

 

v   Basics:

 

·       Program must be brought (from disk)  into Main memory to run

·       Main memory and registers are the only storage the CPU can access directly

·       Register accessed in one CPU clock cycle (or less)

·       Main memory can take many cycles

·       Cache sits between main memory and CPU registers

·       Protection of memory required to ensure correct operation

 

Base and Limit Registers

 

 

 

 

Binding of Instructions and Data to Memory

 

Address binding of instructions and data to memory addresses can happen at three different stages:

ŕ Compile time:  If memory location known a priori, absolute code can be generated; must recompile code if starting location changes

ŕ Load time:  Must generate relocatable code if memory location is not known at compile time

ŕ Execution time:  Binding delayed until run time if the process can be moved during its execution from one memory segment to another. 

Need hardware support for address maps (e.g., base and limit registers)

 

 

Multistep Processing of a User Program

 

 

 

Logical vs. Physical Address Space

 

Logical address space bound to a separate physical address space is central concept in memory management

·       Logical address – generated by the CPU; also referred to as virtual address

·       Physical address – address seen by the memory unit

 

Memory-Management Unit (MMU)

 

·       Hardware device that maps virtual to physical address

·       The value in the relocation register is added to every address generated by a user process

·       The user program deals with logical addresses; it never sees the real physical addresses

 

 

Dynamic Loading

 

·       Routine is not loaded until it is called

·       Better memory-space utilization; unused routine is never loaded

·       Useful when large amounts of code are needed to handle infrequently occurring cases

 

 

Swapping

 

·       A process can be swapped temporarily out of memory to a backing store, and then brought back for continued execution

·       Backing store – fast disk large enough to accommodate copies of all memory images for all users;

·       Major part of swap time is transfer time; directly proportional to the amount of memory swapped

 

 

 

 

Hardware Support for Relocation and Limit Registers

 

Relocation registers used to protect user processes from each other, and from changing operating-system code and data

·       Base register contains value of smallest physical address

·       Limit register contains range of logical addresses – each logical address must be less than the limit register

·       MMU maps logical address dynamically

 

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v   Multiple-partition:

 

Multiple-partition allocation

 

·       Hole  – block of available memory; holes of various size are scattered throughout memory

When a process arrives, it is allocated memory from a hole large enough to accommodate it

·       Operating system maintains information about:

§  allocated partitions   

§  free partitions (hole)

 

 

How to satisfy a request of size n  from a list of free holes

 

ŕ First-fit:    Allocate the first hole that is big enough

 

ŕ Best-fit:    Allocate the smallest hole that is big enough;

·       Must search entire list, unless ordered by size 

·       Produces the smallest leftover hole

 

ŕ Worst-fit:  Allocate the largest hole;

·       Must also search entire list 

·       Produces the largest leftover hole

 

Fragmentation

 

·       External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous

·       Reduce external fragmentation by compaction

ŕ Shuffle memory contents to place all free memory together in one large block

ŕ Compaction is possible only if relocation is dynamic, and is done at execution time

ŕ I/O problem

§  Latch job in memory while it is involved in I/O

§  Do I/O only into OS buffers

 

v   Paging:

 

·       Logical address space of a process can be noncontiguous; process is allocated physical memory whenever available

·       Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes)

·       Divide logical memory into blocks of same size called pages

·       Keep track of all free frames

·       To run a program of size n pages, need to find n free frames and load program

·       Set up a page table to translate logical to physical addresses

·       Produce Internal fragmentation

 

Address Translation Scheme

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Address generated by CPU is divided into:

 

·        Page number (p) – used as an index into a page table which contains base address of each page in physical memory

·        Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit

 

For given logical address space 2m and page size 2n

 

 

 

 

 

 

 

Implementation of Page Table

 

·       Page table is kept in main memory

·       Page-table base register (PTBR) points to the page table

·       Page-table length register (PRLR) indicates size of the page table

·       In this scheme every data/instruction access requires two memory accesses. 

One for the page table and one for the data/instruction.

·       The two memory access problem can be solved by the use of a special fast-lookup hardware cache

called Associative Memory or Translation Look-aside Buffers (TLBs)

 

 

 

Effective Access Time

 

·       Associative Lookup = e time unit

·       Assume memory cycle time is 1 microsecond

·       Hit ratio = a   percentage of times that a page number is found in the associative registers;

·       Effective Access Time (EAT):

EAT = (1 + e) a + (2 + e)(1 – a)

= 2 + e – a

   For example: If a = .9 and e = .1 then EAT = 1.2

 

Shared Pages

 

·       Shared code

o   One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers)

o   Shared code must appear in same location in the logical address space of all processes

 

·       Private code and data

o   Each process keeps a separate copy of the private code and data

o   The pages for the private code and data can appear anywhere in the logical address space

 

Shared Pages Example

 

 

 

v   Structure of the Page Table:

 

·       Hierarchical Paging

·       Hashed Page Tables

·       Inverted Page Tables

 

Two-Level Page-Table Scheme

 

 

 

Two-Level Paging Example

 

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·        A logical address (on 32-bit machine with 1K page size) is divided into:

o   a page number consisting of 22 bits

o   a page offset consisting of 10 bits

·        Since the page table is paged, the page number is further divided into:

o   a 12-bit page number

o   a 10-bit page offset

·        Thus, a logical address is shown above, where pi is an index into the outer page table,

and p2 is the displacement within the page of the outer page table

 

Hashed Page Tables

 

·       Common in address spaces > 32 bits

·       The virtual page number is hashed into a page table

o   This page table contains a chain of elements hashing to the same location

·       Virtual page numbers are compared in this chain searching for a match

o   If a match is found, the corresponding physical frame is extracted

 

 

 

v   Segmentation:

 

Memory-management scheme that supports user view of memory

A program is a collection of segments

 

Example of Segmentation