Thinking ahead, we might realize that we won't always want to compile with the flags “ -g -DDEBUG ” (the significance of which will be introduced in the debugging section).

We can make our makefile more flexible by gathering things that might need to be changed later into a symbol. make allows us to define symbols like this

SymbolName=string

and later use that symbol like this: $(SymbolName).

So we could modify our makefile as follows:

# Macro definitions for "standard" language compilations
# 
#  First, define special compilation flags. These may change when
#  we're done testing and debugging.
CPPFLAGS=-g -DDEBUG
# 

# 
# Targets:
# 
progA: utilities.o progA1.o progA2.o
        g++ $(CPPFLAGS) utilities.o progA1.o progA2.o
        mv a.out progA
  
progB: utilities.o progB1.o
        g++ $(CPPFLAGS) utilities.o progB1.o
        mv a.out progB
  
utilities.o: utilities.c utilities.h
        g++ $(CPPFLAGS) -c utilities.c
  
progA1.o: progA1.cpp utilities.h progA1.h
        g++ $(CPPFLAGS) -c progA1.cpp
  
progA2.o: progA2.cpp utilities.h progA1.h
        g++ $(CPPFLAGS) -c progA2.cpp
  
progB1.o: progB1.cpp
        g++ $(CPPFLAGS) -c progB1.cpp

Makefiles can be simplified by introducing default rules for forming one kind of file from another. Here is an equivalent makefile that defines appropriate default rules:

# Macro definitions for "standard" language compilations
# 
#  First, define special compilation flags. These may change when
#  we're done testing and debugging.
CPPFLAGS=-g -DDEBUG
# 
#  The following is "boilerplate" to set up the standard compilation
#  commands:
.SUFFIXES:
.SUFFIXES: .cpp .c .cpp .h .o
.c.o: ; gcc $(CPPFLAGS) -c $*.c
.cpp.o: ; g++ $(CPPFLAGS) -c $*.cpp
# 
# Targets:
# 
progA: utilities.o progA1.o progA2.o
        g++ $(CPPFLAGS) utilities.o progA1.o progA2.o
        mv a.out progA
  
progB: utilities.o progB1.o
        g++ $(CPPFLAGS) utilities.o progB1.o
        mv a.out progB
  
utilities.o: utilities.c utilities.h
  
progA1.o: progA1.cpp utilities.h progA1.h
  
progA2.o: progA2.cpp utilities.h progA1.h
  
progB1.o: progB1.cpp

In the “SUFFIXES” area, standard commands are defined for producing a .o file from a .c or .cpp file. Of course these standard commands simply invoke the C or C++ compilers. Command lines are not needed if the standard commands from the “Suffixes” area can be used to build the desired file.

So far, we have talked about using make exclusively with compilation. But a makefile can control almost any sequence of operations that build one kind of file out of others.

Certain conventions have arisen that you will find useful in designing your own makefiles and in using the makefiles of others. Most of these involve certain “artificial” targets that you can use when issuing the make command.

These are just conventions. They don't happen automatically, but most people who design makefiles set them up to work this way.

We can bring our sample makefile into conformity with these conventions as follows:

# Macro definitions for "standard" language compilations
# 
#  First, define special compilation flags. These may change when
#  we're done testing and debugging.
CPPFLAGS=-g -DDEBUG
# 
#  The following is "boilerplate" to set up the standard compilation
#  commands:
.SUFFIXES:
.SUFFIXES: .cpp .c .cpp .h .o
.c.o: ; gcc $(CPPFLAGS) -c $*.c
.cpp.o: ; g++ $(CPPFLAGS) -c $*.cpp
# 
# Targets:
# 
all: progA progB

clean:
	rm progA progB *.o

progA: utilities.o progA1.o progA2.o
        g++ $(CPPFLAGS) utilities.o progA1.o progA2.o
        mv a.out progA
  
progB: utilities.o progB1.o
        g++ $(CPPFLAGS) utilities.o progB1.o
        mv a.out progB
  
utilities.o: utilities.c utilities.h
  
progA1.o: progA1.cpp utilities.h progA1.h
  
progA2.o: progA2.cpp utilities.h progA1.h
  
progB1.o: progB1.cpp

When you are faced with the task of writing your own makefiles, the best way to start is to

Now, creating a makefile may seem like a lot of trouble the first time that you want to compile your program. The payoff comes while you are testing and debugging, and find yourself making changes to two or three files and then needing to recompile. Which files do you really need to recompile? It can be hard to remember some times, and the errors resulting from an incorrect guess may be hard to understand. make eliminates this problem (as well as just being easier to type than a whole series of recompilation commands). (This is why, when you give the M-x compile command in emacs, the default compilation command is “make” rather than a direct use of any particular compiler.)

Most of the details of generating a makefile can be automated. The gcc/g++ compiler, for example, will actually write out the makefile rules that would determine when a given .c or .cpp file needs to be recompiled. I've used this idea in this “self-constructing” Makefile. To use it, copy it into your working directory where you keep the source code files for any single program. Your copy must be named “Makefile”. Edit your copy of the file to supply the appropriate program name, list of source code files needed for that program, and to indicate whether the final step (linking) should be done with the C (gcc) or C++ (g++) compiler.

Now you can compile your program by saying make, and clean up afterwards with make clean.

As you continue to work with your code, just remember to keep the OBJS list in the Makefile up to date.